A semiconductor memory device may include a pad portion through which commands and addresses are received for input and output operations of data. The pad portion may be disposed at a central region or an edge region of the semiconductor device when viewed from a plan view. Recently, in the semiconductor memory device employed in mobile systems, the commands and the addresses may be received through a first pad portion located at a first edge region of a semiconductor substrate and the data and data strobe signals are received through a second pad portion located at a second edge region of the semiconductor substrate. The first edge region may be spaced apart from the second edge region.
FIG. 1 is a block diagram illustrating a configuration of a typical semiconductor memory device.
As illustrated in FIG. 1, the typical semiconductor memory device may be configured to include a first edge region 41, a second edge region 42 and a core region 43. The first edge region 41 may include a column enable signal generator 412 for generating a column enable signal YI_EN that has pulses for executing a column operation in a write mode in response to a write command WT_CMD inputted through a first pad portion 411. The second edge region 42 may include a data input portion 422 for receiving data DIN generated in synchronization with a data strobe signal DQS outputted from a second pad portion 421 to transmit the data DIN to the core region 43. The core region 43 may include a column control portion 431 for controlling an operation that stores the data DIN in memory cells in response to the column enable signal YI_EN in a write mode. The column enable signal YI_EN may be enabled to generate a column selection signal for controlling an operation that transmits data on local input/output lines to bit lines electrically connected to the memory cells.
The typical semiconductor memory device described above may store the data DIN outputted from the second edge region 42 in the memory cells disposed in the core region 43 in response to the column enable signal YI_EN in a write mode.
In the event that the column control portion 431 is disposed to be closer to the first edge region 41 than a distance between the column control portion 431 and the second edge region 42, the column enable signal YI_EN transmitted through a first path P1 may reach the column control portion 431 before the data DIN transmitted through a second path P2 reaches the column control portion 431. That is, signals of the local input/output lines may be transmitted to the bit lines before the data DIN are transmitted to the local input/output lines. Accordingly, the data DIN and the column enable signal YI_EN can be synchronously inputted to the column control portion 431 by appropriately delaying the column enable signal YI_EN. However, in such a case, there may be some difficulties in adjusting the timings of the data DIN and the column enable signal YI_EN according to the position of the column control portion 431.